ltc1069-7 1 10697fa typical application description linear phase 8th order lowpass filter the ltc ? 1069-7 is a monolithic, clock-tunable, linear phase, 8th order lowpass ? lter. the amplitude response of the ? lter approximates a raised cosine ? lter with an alpha of one. the gain at the cutoff frequency is C 3db and the attenuation at twice the cutoff frequency is 43db. the single 5v supply, linear phase 100khz lowpass filter l , lt, ltc and ltm are registered trademarks of linear technology corporation. features applications n 8th order, linear phase filter in so-8 package n raised cosine amplitude response n C 43db attenuation at 2 f cutoff n wideband noise: 140v rms n operates from single 5v supply to 5v power supplies n clock-tunable to 200khz with 5v supplies n clock-tunable to 120khz with single 5v supply n digital communication filter n antialiasing filter with linear phase n smoothing filters agnd v + nc v in v in v out v out v C nc clk ltc1069-7 f clk = 2.5mhz 5v 0.47 f 0.1 f 1069-7 ta01 frequency (khz) 10 C70 gain (db) C60 C50 C40 C30 10 100 1000 1069-7 ta02 C20 C10 0 cutoff frequency of the ltc1069-7 is set by an external clock and is equal to the clock frequency divided by 25. the ratio of the internal sampling frequency to the cutoff frequency is 50:1 that is, the input signal is sampled twice per clock cycle to lower the risk of aliasing. the ltc1069-7 can be operated from a single 5v supply up to dual 5v supplies. the gain and phase response of the ltc1069-7 can be used in digital communication systems where pulse shaping and channel bandwidth limiting must be carried out. any system that requires an analog ? lter with linear phase and sharper roll off than conventional bessel ? lters can use the ltc1069-7. the ltc1069-7 has a wide dynamic range. with 5v supplies and an input range of 0.1v rms to 2v rms , the signal-to-(noise + thd) ratio is 60db. the wideband noise of the ltc1069-7 is 140v rms . unlike other ltc1069-x lters, the typical passband gain of the ltc1069-7 is equal to ?v/v. the ltc1069-7 is available in an so-8 package. other ? lter responses with lower power/speed speci? cations can be obtained. please contact ltc marketing. frequency response
ltc1069-7 2 10697fa pin configuration absolute maximum ratings total supply voltage (v + to v ? ) ............................... 12v power dissipation .............................................. 400mw operating temperature range ltc1069-7c ............................................ 0c to 70c ltc1069-7i ......................................... ? 40c to 85c storage temperature ..............................?65c to 150c lead temperature (soldering, 10 sec) .................. 300c 1 2 3 4 8 7 6 5 top view v out v ? nc clk agnd v + nc v in s8 package 8-lead plastic so t jmax = 125c,
ltc1069-7 3 10697fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: phase deviation = 1/2(phase at 0hz C phase at f cutoff ) C (phase at 0hz C phase at 0.5f cutoff ) phase at 0hz = 180 (guaranteed by design) electrical characteristics the l denotes speci? cations which apply over the full operating temperature range. f cutoff is the ? lters cutoff frequency and is equal to f clk /25. the f clk signal level is ttl or cmos (max clock rise or fall time 1s), r l = 10k, t a = 25c, unless otherwise speci? ed. all ac gains are measured relative to the passband gain. symbol conditions min typ max units gain at 1.5f cutoff v s = 5v, f clk = 2.5mhz f test = 150khz, v in = 1v rms C19 C16.5 C14 db db v s = 4.75v, f clk = 500khz f test = 30khz, v in = 0.5v rms C20 C18.1 C17 db db gain at 2.0f cutoff v s = 5v, f clk = 2.5mhz f test = 200khz, v in = 1v rms C55 C43 C38 db db v s = 4.75v, f clk = 500khz f test = 40khz, v in = 0.5v rms C48 C41 C39 db db gain at 5.0f cutoff v s = 4.75v, f clk = 500khz f test = 100khz, v in = 0.5v rms C70 C59 C55 db gain at f cutoff (160khz) v s = 5v, f clk = 4mhz f test = 160khz, v in = 1v rms C2.1 db phase at 0.5f cutoff v s = 5v, f clk = 2.5mhz f test = 50khz C35 C30.5 C25 deg phase at f cutoff v s = 5v, f clk = 2.5mhz f test = 100khz C240 C235 C230 deg passband phase deviation from linear phase (note 1) v s = 5v, f clk = 500khz C3.0 deg output dc offset (input at gnd) v s = 5v, f clk = 500khz v s = 4.75v, f clk = 400khz 50 25 125 mv mv output voltage swing v s = 5v, i source /i sink 1ma, r l = 10k v s = 4.75v, i source /i sink 1ma, r l = 10k l l 3.5 2.6 4.0 3.6 v v p-p power supply current v s = 5v, f clk = 500khz l 18 26 29 ma ma v s = 4.75v, f clk = 400khz l 13 15 16.5 ma ma example: an ltc1069-7 has phase at 0.5f cutoff = C 30.5 and phase at f cutoff = C235. passband phase deviation from linear phase = 1/2[180 C (C235)] C [(180 C (C30.5)] = C3
ltc1069-7 4 10697fa typical performance characteristics passband gain vs frequency frequency (khz) 1 gain (db) 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 C2.5 C3.0 C3.5 C4.0 17 1069-7 g01 5 3 7 11 15 19 9 13 21 v s = 5v f clk = 500khz f c = 20khz v in = 2v rms frequency (khz) 41 gain (db) C40 C42 C44 C46 C48 C50 C52 C54 C56 C58 C60 73 1069-7 g03 49 45 53 61 69 77 57 65 81 v s = 5v f clk = 500khz f c = 20khz v in = 2v rms stopband gain vs frequency frequency (khz) gain (db) 10 0 C10 C20 C30 C40 C50 25 29 33 37 1069-7 g02 41 23 21 27 31 35 39 v s = 5v f clk = 500khz f c = 20khz v in = 2v rms transition band gain vs frequency frequency (khz) 1 gain (db) 10 0 C10 C20 C30 C40 C50 C60 10 100 1069-7 g04 v s = 5v f clk = 250khz f c = 10khz v in = 1v rms frequency (khz) 20 gain (db) 100 3 0 C3 C6 C9 C12 C15 C18 1069-7 g05 60 140 40 120 80 160 180 200 f clk = 2.5mhz f clk = 3.5mhz f clk = 3mhz f clk = 4mhz f clk = 4.5mhz f clk = 5mhz v s = 5v v in = 2v rms frequency (khz) 10 gain (db) 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 C2.5 C3.0 C3.5 C4.0 130 1069-7 g06 40 70 100 160 t a = 85c t a = C40c t a = 25c v s = 5v f clk = 4mhz f c = 160khz v in = 2v rms frequency (khz) 10 gain (db) 10 0 C10 C20 C30 C40 C50 C60 30 110 150 1069-7 g07 90 190 210 50 70 130 170 v s = 5v v s = 5v f clk = 2mhz f c = 80khz v in = 0.5v rms frequency (khz) 20 gain (db) 100 3 0 C3 C6 C9 C12 C15 C18 1069-7 g08 60 140 40 120 80 160 180 200 f clk = 1.5mhz f clk = 2mhz f clk = 2.5mhz f clk = 3mhz v s = 5v v in = 1v rms frequency (khz) 10 gain (db) 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 C2.5 C3.0 C3.5 C4.0 30 50 60 100 1069-7 g09 20 40 70 80 90 t a = 85c t a = C40c t a = 25c v s = 5v f clk = 2.5mhz f c = 100khz v in = 1v rms passband gain vs clock frequency gain vs frequency passband gain vs frequency passband gain vs clock frequency gain vs supply voltage passband gain vs frequency
ltc1069-7 5 10697fa typical performance characteristics phase matching vs frequency thd + noise vs input (v p-p ) thd + noise vs frequency transient response output offset vs clock frequency output voltage swing vs temperature passband gain and phase vs frequency passband gain and delay vs frequency frequency (khz) 0 gain (db) phase (deg) 2 1 0 C1 C2 C3 C4 C5 C6 C7 C8 180 135 90 45 0 C45 C90 C135 C180 C225 C270 80 1069-7 g10 20 10 30 50 70 90 40 60 100 gain phase v s = 5v f clk = 2.5mhz f c = 100khz frequency (khz) 0 gain (db) delay (s) 2 1 0 C1 C2 C3 C4 C5 C6 C7 C8 13.5 13.0 12.5 12.0 11.5 11.0 80 1069-7 g12 20 10 30 50 70 90 40 60 100 gain delay v s = 5v f clk = 2.5mhz f c = 100khz frequency (f cutoff /frequency) 0 phase difference (deg) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0.8 1069-7 g11 0.2 0.1 0.3 0.5 0.7 0.9 0.4 0.6 1.0 70c 25c v s = 5v f clk 2.5mhz phase difference between any two units (sample of 20 representative units) input (v p-p ) 0.1 thd + noise (db) C40 C45 C50 C55 C60 C65 C70 C75 110 1609-7 g13 v s = 5v v s = 5v f clk = 1mhz f c = 40khz f in = 1khz frequency (khz) 1 thd + noise (db) C40 C45 C50 C55 C60 C65 C70 C75 C80 10 100 1069-7 g14 f clk = 2.5mhz f c = 100khz v s = 5v, v in = 1v p-p v s = 5v, v in = 2v p-p 1v/div v s = 5v f clk = 500khz f cutoff = 20khz v in = 4v p-p square wave at 1khz 0.1ms/div 1069-7 g15 clock frequency (mhz) 0.25 output offset (mv) C10 C15 C20 C25 C30 C35 C40 C45 C50 4.25 1069-7 g16 1.25 2.25 3.25 5.25 v s = 5v v s = 5v temperature (c) C40 1.0 voltage swing (v) 1.2 4.3 0 40 60 1069-7 g17 1.1 4.2 4.1 C20 20 80 100 v s = 5v (agnd at 2.5v) f clk = 500khz f cutoff = 20khz r l = 10k i source /i sink 1ma
ltc1069-7 6 10697fa typical performance characteristics output voltage swing vs temperature supply current vs supply voltage supply current vs clock frequency pin functions agnd (pin 1): analog ground. the quality of the analog signal ground can affect the ? lter performance. for either single or dual supply operation, an analog ground plane surrounding the package is recommended. the analog ground plane should be connected to any digital ground at a single point. for dual supply operation, pin 1 should be connected to the analog ground plane. for single supply operation, pin 1 should be bypassed to the analog ground plane with a capacitor 0.47f or larger. an internal resistive divider biases pin 1 to half the total power supply. pin 1 should be buffered if used to bias other ics. figure 1 shows the connections for single supply operation. v + , v C (pins 2, 7): power supplies. the v + (pin 2) and v C (pin 7) should be bypassed with a 0.1f capacitor to an adequate analog ground. the ? lters power supplies should be isolated from other digital or high voltage analog supplies. a low noise linear supply is recommended. using switching power supplies will lower the signal-to-noise ratio of the ? lter. unlike previous monolithic ? lters, the power supplies can be applied in any order, that is, the positive supply can be applied before the negative supply and vice versa. figure 2 shows the connections for dual supply operation. nc (pins 3, 6): no connection. pins 3 and 6 are not connected to any internal circuitry; they should be tied to ground. v in (pin 4): filter input. the ? lter input pin is internally connected to the inverting inputs of two op amps through a 36k resistor for each op amp. this parallel combination creates an 18k input impedance. temperature (c) C40 C4.7 voltage swing (v) C4.5 4.2 0 40 60 1069-7 g18 C4.6 4.1 4.0 C20 20 80 100 v s = 5v f clk = 2.5mhz f cutoff = 100khz r l = 10k i source /i sink = 1ma supply voltage (v) 0 supply current (ma) 12 1069-7 g19 36 25 20 15 10 5 0 45 85c C40c 25c f clk = 10hz clock frequency (mhz) 0.25 1.25 2.25 3.25 4.25 5.25 supply current (ma) 1069-7 g20 22 21 20 19 18 17 16 15 14 13 12 11 10 v s = 5v v s = 5v 1069-7 f01 1k v + ltc1069-7 clock source 0.47f 0.1f analog ground plane 8 7 6 5 1 2 3 4 star system ground digital ground plane agnd v + nc v in v out v C nc clk v out v in figure 1. connections for single supply operation
ltc1069-7 7 10697fa clk (pin 5): clock input. any ttl or cmos clock source with a square wave output and 50% duty cycle (10%) is an adequate clock source for the device. the power supply for the clock source should not necessarily be the ? lters power supply. the analog ground of the ? lter should only be connected to the clocks ground at a single point. table 1 shows the clocks low and high level threshold value for v C 1069 f02 1k v + ltc1069-7 clock source 0.1f analog ground plane 8 7 6 5 agnd v + nc v in 1 2 3 4 v out v C nc clk star system ground digital ground plane v in 0.1f v out figure 2. connections for dual supply operation pin functions a dual or single supply operation. a pulse generator can be used as a clock source provided the high level on-time is greater than 0.42s (v s = 5v). sine waves less than 100khz are not recommended for clock sources because excessive slow clock rise or fall times generate internal clock jitter. the maximum clock rise or fall time is 1s. the clock signal should be routed from the right side of the ic package to avoid coupling into any input or output analog signal path. a 1k resistor between the clock source and the clock input (pin 5) will slow down the rise and fall times of the clock to further reduce charge coupling, figure 1. table 1. clock source high and low thresholds power supply high level low level dual supply = 5v 1.5v 0.5v single supply = 10v 6.5v 5.5v single supply = 5v 1.5v 0.5v v out (pin 8): filter output. pin 8 is the output of the ? lter, and it can source 23ma or sink 16ma. the total harmonic distortion of the ? lter will degrade when driving coaxial cables or loads less than 20k without an output buffer. applications information temperature behavior the power supply current of the ltc1069-7 has a positive temperature coef? cient. the gbw product of its internal op amps is nearly constant and the speed of the device does not degrade at high temperatures. clock feedthrough the clock feedthrough is de? ned as the rms value of the clock frequency and its harmonics that are present at the ? lters output (pin 8). the clock feedthrough is tested with the input (pin 4) shorted to the agnd pin and depends on pc board layout and on the value of the power supplies. with proper layout techniques the values of the clock feedthrough are shown on table 2. table 2. clock feedthrough v s clock feedthrough 5v 400v rms 5v 850v rms any parasitic switching transients during the rising and falling edges of the incoming clock are not part of the clock feedthrough speci? cations. switching transients have frequency contents much higher than the applied clock; their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. the clock feedthrough can be reduced by adding a single rc lowpass ? lter at the output (pin 8) of the ltc1069-7.
ltc1069-7 8 10697fa wideband noise the wideband noise of the ? lter is the total rms value of the devices noise spectral density and determines the operating signal-to-noise ratio. most of the wideband noise frequency contents lie within the ? lter passband. the wideband noise cannot be reduced by adding post ? ltering. the total wideband noise is nearly independent of the clock frequency and depends slightly on the power supply voltage (see table 3). the clock feedthrough speci? cations are not part of the wideband noise. table 3. wideband noise v s clock feedthrough 4.75v 125v rms 5v 140v rms aliasing aliasing is an inherent phenomenon of sampled data systems and it occurs for input frequencies approaching the sampling frequency. the internal sampling frequency of the ltc1069-7 is 50 times its f cutoff frequency. for instance if a 48khz, 100mv rms signal is applied at the applications information input of an ltc1069-7 operating with a 50% duty cycle 25khz clock, a 2khz, 741v rms alias signal will appear at the ? lter output. table 4 shows details. table 4. aliasing input frequency v in = 1v rms output level relative to input output frequency aliased frequency f clk /f c = 25:1, f cutoff = 1khz 40khz (or 60khz) C59.9db 10khz 47khz (or 53khz) C54.2db 3khz 48khz (or 52khz) C42.6db 2khz 48.5khz (or 51.5khz) C18.3db 1.5khz 49khz (or 52khz) C2.9db 1.0khz 49.5khz (or 50.5khz) C0.65db 0.5khz speed limitations to avoid op amp slew rate limiting, the signal amplitude should be kept below a speci? ed level as shown in table 5. table 5. maximum v in vs v s and clock v s maximum clock maximum v in 5v 2.5mhz 340mv rms (f in 200khz) 5v 4.5mhz 1.2v rms (f in 400khz)
ltc1069-7 9 10697fa .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) s 45 0C 8 typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) package description
ltc1069-7 10 10697fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 ltc 0309 rev a ? printed in usa related parts part number description comments ltc1064-3 linear phase, bessel 8th order filter f clk /f c = 75/1 or 150/1, very low noise ltc1064-7 linear phase, 8th order lowpass filter f clk /f c = 50/1 or 100/1, f c(max) = 100khz ltc1164-7 low power, linear phase lowpass filter f clk /f c = 50/1 or 100/1, i s = 2.5ma, v s = 5v ltc1264-7 linear phase 8th order lowpass filter f clk /f c = 25/1 or 50/1, f c(max) = 200khz agnd v + nc v in v in v out v C nc clk ltc1069-7 f clk 5mhz 0.1f 1069-7 ta03 + C v out lt ? 1354 5v 0.1f C5v 1f 10k 5v C5v 10k 51pf 0.1f 0.1f clock tunable, noninverting, linear phase 8th order filter to 200khz f cutoff typical application
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